Optical sensor arrangement and method for light sensing

ABSTRACT

An optical sensor arrangement comprises a photodiode ( 11 ), an integrator ( 12 ) with an integrator input ( 15 ) coupled to the photodiode ( 11 ), a comparator ( 13 ) with a first input ( 18 ) coupled to an integrator output ( 16 ) of the integrator ( 12 ), and a reference capacitor circuit ( 14 ) that is coupled to the integrator input ( 15 ) and is designed to provide a charge package to the integrator input ( 15 ). In a start phase (A), charge packages are provided to the integrator input ( 15 ), until a comparator input voltage (VIN) at the first input ( 18 ) of the comparator ( 13 ) crosses a comparator switching point.

BACKGROUND OF THE INVENTION

The present patent application is related to an optical sensorarrangement and to a method for light sensing.

An optical sensor arrangement often comprises a photodiode as a lightdetector and measures a photocurrent flowing through the photodiode. Theoptical sensor arrangement may convert the photocurrent into a digitalsignal. For example, the optical sensor arrangement may be realized as alight-to-frequency circuit, also called light-to-frequency machine,abbreviated LTF machine. A starting point of such an optical sensorarrangement has a large influence on the accuracy of the detecteddigital signal.

SUMMARY OF THE INVENTION

In an embodiment, an optical sensor arrangement comprises a photodiode,an integrator, a comparator and a reference capacitor circuit. Anintegrator input of the integrator is coupled to the photodiode. A firstinput of the comparator is coupled to an integrator output of theintegrator. The reference capacitor circuit is coupled to the integratorinput and is designed to provide a charge package to the integratorinput. In a start phase, charge packages are provided to the integratorinput, until a comparator input voltage at the first input of thecomparator crosses a comparator switching point of the comparator.

Advantageously, at the end of the start phase, the comparator inputvoltage at the first input of the comparator is very near to thecomparator switching point. Thus, the comparator input voltage is welldefined. After the comparator input voltage crosses the comparatorswitching point, no more charge packages are added to the integratorinput in the start phase.

The reference capacitor circuit may comprise a reference source forproviding a first reference voltage.

In an embodiment, the comparator input voltage at the first input of thecomparator is generated by the integrator and is tapped at theintegrator output. Thus, the comparator input voltage is equal to anoutput voltage of the integrator.

In an embodiment, one charge package of the charge packages provided inthe start phase typically results in a predetermined voltage differenceof the comparator input voltage. Advantageously, in the start phase, thecomparator input voltage is brought close to the comparator switchingpoint either from the positive side or the negative side. At the end ofthe start phase, the deviation of the comparator input voltage from thecomparator switching point may be less than the predetermined voltagedifference.

In an embodiment, at the beginning of the start phase, the comparatorinput voltage may be higher than the comparator switching point. Thus,the charge packages are set in such a manner that the comparator inputvoltage is reduced, until the comparator input voltage crosses thecomparator switching point and becomes equal or smaller than thecomparator switching point.

In an alternative embodiment, at the beginning of the start phase, thecomparator input voltage is smaller than the comparator switching pointand the charge packages are set in such a manner that the comparatorinput voltage is increased, until the comparator input voltage crossesthe comparator switching point and becomes equal or larger than thecomparator switching point.

In an embodiment, a measuring phase follows the start phase. In themeasuring phase, the photodiode provides a photocurrent to theintegrator input.

In an embodiment, the optical sensor arrangement comprises a firstswitch that couples the photodiode to the integrator input. In the startphase, the first switch is set in a non-conducting state. In themeasuring phase, the first switch is set in a conducting state. Themeasuring phase follows the start phase. Thus, the photodiodeexclusively provides a photocurrent to the integrator input in themeasuring phase and not in the start phase.

In an embodiment, the optical sensor arrangement comprises a secondswitch that couples the photodiode to a reference potential terminal, avoltage source or a reference source. In the start phase, the secondswitch is set in a conducting state. In the measuring phase, the secondswitch is set in a non-conducting state.

In an alternative embodiment, in the start phase, the first switch maybe set in a conducting state and the second switch may be set in anon-conducting state. The photodiode may provide the photocurrent to theintegrator input in the measuring phase and in the start phase. Apossible error caused by the photocurrent may be low in case of a shortduration of the start phase and/or low light conditions.

In an embodiment, the reference capacitor circuit is designed toselectively provide at least two different charge values of the chargepackage to the integrator input.

The reference capacitor circuit may comprise a reference capacitor.

In an embodiment, the reference capacitor is controllable and can obtainat least two different capacitance values. The at least two differentcapacitance values can be set by a capacitor control signal.

In an embodiment, the reference capacitor circuit comprises a firstreference switch coupling a first electrode of the reference capacitorto the integrator input, a second reference switch coupling the firstelectrode of the reference capacitor to a reference terminal, a thirdreference switch coupling a second electrode of the reference capacitorto a reference source terminal and a fourth reference switch couplingthe second electrode of the reference capacitor to the referenceterminal.

In an embodiment, at least two different reference voltages canselectively be provided to the reference source terminal. Thus, byselecting one reference voltage out of the at least two differentreference voltages, the charge value of the charge package provided bythe reference capacitor circuit is set. Optionally, the at least twodifferent reference voltages have different amounts but the same sign.

In an alternative embodiment, the third reference switch provides afirst reference voltage to the second electrode of the referencecapacitor. The first reference voltage is tapped at the reference sourceterminal. The reference capacitor circuit comprises a fifth referenceswitch that provides a second reference voltage to the second electrodeof the reference capacitor.

The reference capacitor circuit may comprise a charge voltage divider atwhich the at least two different reference voltages can be tapped.

In an embodiment, the integrator comprises an amplifier having an inputcoupled to the integrator input and an output coupled to the integratoroutput.

In an embodiment, the integrator comprises an integrator capacitor thatis coupled to the input of the amplifier and to the output of theamplifier.

In an embodiment, the integrator comprises an integrator switch couplingthe integrator capacitor to the output of the amplifier.

In an embodiment, the integrator comprises a further integrator switchcoupling a node between the integrator capacitor and the integratorswitch to a voltage terminal.

In an embodiment, the optical sensor arrangement comprises a de-chargingswitch coupling the integrator input to a reference potential terminal.

In an embodiment, a comparator threshold voltage is applied to a secondinput of the comparator for setting the comparator switching point. Forexample, the optical sensor arrangement may comprises a voltage sourcecoupled to the second input of the comparator for setting the comparatorswitching point.

In an embodiment, an optical sensor arrangement comprises a photodiode,an integrator with an integrator input, a first switch that couples thephotodiode to the integrator input, a comparator with a first inputcoupled to an integrator output of the integrator, a control circuithaving an input connected to an output of the comparator, and areference capacitor circuit that is coupled to the integrator input andis designed to provide a charge package to the integrator input. Acomparator input voltage is generated by the integrator and is tapped atthe first input of the comparator. The comparator generates a comparatorsignal that is provided to the control circuit. In a start phase, chargepackages are provided to the integrator input by the reference capacitorcircuit, until the comparator input voltage crosses a comparatorswitching point of the comparator.

In a further development, the control circuit is connected on its outputside to the reference capacitor circuit. In the start phase, the controlcircuit may stop providing a further charge package to the integratorinput, when the comparator input voltage crosses the comparatorswitching point of the comparator. In the start phase, the controlcircuit may control the reference capacitor circuit such that thereference capacitor circuit stops providing a further charge package tothe integrator input, when the comparator input voltage crosses thecomparator switching point of the comparator.

In an embodiment, a method for light sensing comprises that in a startphase charge packages are provided by a reference capacitor circuit toan integrator input of an integrator, until a comparator input voltageat a first input of a comparator crosses a comparator switching point.The first input of the comparator is coupled to an integrator output ofthe integrator. Moreover, in a measuring phase, a photocurrent isprovided by a photodiode to the integrator input.

Thus, the comparator input voltage only differs to a small extent fromthe comparator switching point at the end of the start phase.Advantageously, the integrator comparator and the reference capacitorcircuit are operating in the start phase, thus any transient signalsgenerated by switching on the comparator, the integrator or thereference capacitor circuit are avoided at the transition from the startphase to the measuring phase.

In an embodiment, if at the beginning of the start phase the comparatorinput voltage is only slightly above the comparator switching point,only one charge package is provided to the integrator input.

In an embodiment, a control circuit of the optical sensor arrangementdetects the crossing of the comparator switching point and stopsproviding a further charge package to the integrator input in the startphase.

In an embodiment, the photocurrent of the photodiode is not provided tothe integrator input in the start phase.

In an embodiment, the photocurrent is provided to the integrator inputin the measuring phase resulting in a rise of the comparator inputvoltage above the comparator switching point. A comparator signalgenerated at the output of the comparator triggers the referencecapacitor circuit such that the reference capacitor circuit provides acharge package to the integrator input. A high value of the photocurrentresults in a high number of pulses of the comparator signal and a smalldistance of the pulses of the comparator signal in the measuring phase.Thus, the comparator signal obtains a high frequency. A low value of thephotocurrent results in a small number of pulses and in a long distanceof the pulses of the comparator signal and thus in a low frequency ofthe comparator signal in the measuring phase. Thus, the number of pulsesof the comparator signal and the frequency of the comparator signal inthe measuring phase is proportional to the value of the photocurrent.The measuring phase has a predetermined integration duration.

Advantageously, the optical sensor arrangement realises a linearityimprovement for the light to frequency machine, abbreviated LTF machine,also called light-to-frequency modulator, abbreviated LTF modulator.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description of figures of exemplary embodiments mayfurther illustrate and explain aspects of the application. Devices andcircuit parts with the same structure and the same effect, respectively,appear with equivalent reference symbols. In so far as devices orcircuit parts correspond to one another in terms of their function indifferent figures, the description thereof is not repeated for each ofthe following figures.

FIGS. 1A and 1B show exemplary embodiments of an optical sensorarrangement.

FIGS. 2 and 3 show exemplary embodiments of timing diagrams of signalsof an optical sensor arrangement.

DETAILED DESCRIPTION

FIG. 1A shows an exemplary embodiment of an optical sensor arrangement10 comprising a photodiode 11, an integrator 12, a comparator 13 and areference capacitor circuit 14. In FIG. 1A, a simple block diagram ofthe LTF machine 10 is illustrated. The integrator 12 comprises anintegrator input 15 and an integrator output 16. The integrator input 15is coupled to the photodiode 11. The integrator output 16 is connectedto a first input 18 of the comparator 13. Moreover, the optical sensorarrangement 10 comprises a control circuit 21 having an input connectedto an output of the comparator 13.

The optical sensor arrangement 10 comprises a first switch 22 that isarranged between the photodiode 11 and the integrator input 15. An anodeof the photodiode 11 is connected to a reference potential terminal 17.A cathode of the photodiode 11 is coupled via the first switch 22 to theintegrator input 15. Moreover, the optical sensor arrangement 10comprises a second switch 23 that couples the photodiode 11 to thereference potential terminal 17. Thus, the second switch 23 couples anode between the first switch 22 and the photodiode 11 to the referencepotential terminal 17. Additionally, a de-charging switch 24 is arrangedbetween the integrator input 15 and the reference potential terminal 17.

The integrator 12 comprises an amplifier 26 and an integrator capacitor27. An input of the amplifier 26 is directly connected to the integratorinput 15. An output of the amplifier 26 is directly connected to theintegrator output 16. The input of the amplifier 26 may be realized asan inverting input. A further input of the amplifier 26 is connected tothe reference potential terminal 17. The further input of the amplifiermay be realized as a non-inverting input. A first electrode of theintegrator capacitor 27 is connected to the integrator input 15 and thusto the input of the amplifier 26. A second electrode of the integratorcapacitor is coupled to the output of the amplifier 26 and thus to theintegrator output 16.

The integrator 12 comprises an integrator switch 28. The integratorswitch 28 couples the second electrode of the integrator capacitor 27 tothe output of the amplifier 26 and thus to the integrator output 16. Anode between the integrator capacitor 27 and the integrator switch 28 iscoupled via a further integrator switch 29 to a voltage terminal 30. Inan example, the voltage terminal 30 may be connected to a second input19 of the comparator 13.

The reference capacitor circuit 14 comprises a reference capacitor 40having a first and a second electrode. A first reference switch 41 ofthe reference capacitor circuit 14 couples the first electrode of thereference capacitor 40 to the integrator input 15. A second referenceswitch 42 couples the first electrode of the reference capacitor 40 to areference terminal 43. Moreover, the reference capacitor circuit 14comprises a third reference switch 44 coupling the second electrode ofthe reference capacitor 40 to a reference source terminal 46.Furthermore, a fourth reference switch 45 of the reference capacitorcircuit 14 couples the second electrode of the reference capacitor 40 tothe reference terminal 43.

The control circuit 21 is connected on its output side to the referencecapacitor circuit 14. Outputs of the control circuit 21 are connected tothe control terminals of the first to the fourth reference switches 41,42, 44, 45, the first switch 22, the second switch 23, the de-chargingswitch 24, the integrator switch 28 and the further integrator switch29. Moreover, the control circuit 21 comprises a signal output 49.

A comparator threshold voltage VCT is applied to the second input 19 ofthe comparator 13. The comparator threshold voltage VCT sets acomparator switching point of the comparator 13. The comparatorthreshold voltage VCT may be equal to the comparator switching point.The comparator 13 generates a comparator signal SC. The comparatorsignal SC is implemented as a light-to-frequency output signal,abbreviated LTF-OUT. The comparator signal SC is provided to the controlcircuit 21. The control circuit 21 generates an output signal SOUT atthe signal output 49 as a function of the comparator signal SC. Thecontrol circuit 21 generates reference control signals S1 to S4, switchcontrol signals SW1 to SW5 and provide said control signals to thecontrol terminals of the switches 22 to 24, 28, 29, 41, 42, 44, 45.

A terminal voltage VC can be tapped at the voltage terminal 30 and isapplied to the further integrator switch 29. A not-shown voltage sourcemay be connected to the voltage terminal 30 and may generate theterminal voltage VC. The voltage source may also be connected to thesecond input 19 of the comparator 13. In this case, the terminal voltageVC may be equal to the comparator threshold voltage VCT.

A reference potential GND can be tapped at the reference potentialterminal 17. The reference potential GND is provided to the furtherinput of the amplifier 26. A reference signal AVSS is provided to thereference terminal 43. The reference signal AVSS may be equal to thereference potential GND. A first reference voltage VR1 is tapped at thereference source terminal 46. The first reference voltage VR1 isprovided to the third reference switch 44.

A comparator input voltage VIN can be tapped at the integrator output 16and, thus, at the first input 18 of the comparator 13. The comparatorsignal SC is a function of the difference between the comparator inputvoltage VIN and the comparator threshold voltage VCT or the comparatorswitching point. If the comparator input voltage VIN is higher than thecomparator threshold voltage VCT or the comparator switching point, thenthe comparator 13 generates the comparator signal SC with a firstlogical value.

In an embodiment, the second input 19 of the comparator 13 is connectedto a voltage source, not shown. The voltage source is arranged betweenthe second input 19 of the comparator 13 and the reference potentialterminal 17. The voltage source generates the comparator thresholdvoltage VCT that sets the comparator switching point of the comparator30.

The comparator threshold voltage VCT may be different from the terminalvoltage VC.

In an alternative, not shown embodiment, the reference capacitor 40 iscontrollable. A capacitor control signal may select one capacitancevalue of at least two different capacitance values of the referencecapacitor 40. Thus, a charge package provided by the reference capacitorcircuit 14 selectively has one of at least two different charge values.

In an embodiment, the comparator 13 may be realized as Schmitt triggercircuit or monostable circuit.

FIG. 1B shows an exemplary embodiment of the optical sensor arrangement10 that is a further development of the optical sensor arrangement shownin FIG. 1A. The optical sensor arrangement 10 comprises a voltage source50 that is connected to the voltage terminal 30. The voltage source 50may be realized as a reference voltage source, e.g. as a bandgapcircuit. The optical sensor arrangement 10 comprises a comparatorvoltage divider 51 coupling the voltage source 50 to the referencepotential terminal 17. The comparator voltage divider 51 comprises twodivider resistors 52, 53. A tap of the comparator voltage divider 51 isbetween the two divider resistors 52, 53 and is connected to the secondinput 19 of the comparator 13. The voltage source 50 is connected to thefurther integrator switch 29.

Thus, the voltage source 50 provides the terminal voltage VC to thefurther integrator switch 29. At the tap of the comparator voltagedivider 51, the comparator threshold voltage VCT is provided that isapplied to the second input 19 of the comparator 13. The comparatorthreshold voltage VCT is smaller than the terminal voltage VC. Thus, atthe beginning of a start phase A that is described below, the comparatorinput voltage VIN is higher than the comparator threshold voltage VCT.

Moreover, the optical sensor arrangement 10 comprises a reference source60 that is connected to the reference source terminal 46. The referencesource 60 may be realized as a reference voltage source, e.g. as abandgap circuit. A reference source divider 61 of the optical sensorarrangement 10 couples the reference source 60 to the referencepotential terminal 17 and comprises two divider resistors 62, 63. A tapof the reference source divider 61 is between the two divider resistors62, 63 and is coupled via a fifth reference switch 64 of the referencecapacitor circuit 14 to the second electrode of the reference capacitor40.

Thus, the reference source 60 generates the first reference voltage VR1that can be provided via the fourth reference switch 44 to the secondelectrode of the reference capacitor 14. At the tap of the referencesource divider 61, a second reference voltage VR2 is generated that canbe provided via the fifth reference switch 64 to the second electrode ofthe reference capacitor 40. The second reference voltage VR2 is smallerthan the first reference voltage VR1.

FIG. 2 shows an exemplary embodiment of a timing diagram of signals ofthe optical sensor arrangement 10 shown in FIGS. 1A and 1B. In FIG. 2,the comparator input voltage VIN, the switch control signal SW5 that isprovided to the second switch 23 and the comparator signal SC are shownas a function of time t. A measuring phase B follows the start phase A.During the start phase A, the switch control signal SW5 has a valuesetting the second switch 23 in a conducting state. Contrary to that, inthe measuring phase B, the switch control signal SW5 has a value settingthe second switch 23 in a non-conducting state. Thus, the photodiode 11provides a photocurrent IP to the reference potential terminal 17 in thestart phase A and applies the photocurrent IP to the integrator input 15in the measuring phase B.

At the beginning of the start phase A, the first integrator switch 29and the de-charge switch 24 are set in a conducting state. Thus, theintegrator capacitor 27 is charged and the terminal voltage VC isapplied between the second and the first electrode of the integratorcapacitor 27. Then, the further integrator switch 30 and the de-chargingswitch 24 are set in a non-conducting state. The integrator switch 28 isset in a conducting state. Thus, the voltage at the second electrode ofthe integrator capacitor 27 is provided via the integrator switch 28 tothe integrator output 16 and consequently to the first input 18 of thecomparator 13. At the beginning of the start phase A, the comparatorinput voltage VIN has a high value. The terminal voltage VC is selectedsuch that the comparator input voltage VIN is higher than the comparatorswitching point. The comparator signal SC obtains a first logical valuethat indicates that the comparator input voltage VIN is higher than thecomparator switching point.

The comparator signal SC is provided to the control circuit 21 thattriggers the reference capacitor circuit 14 such that the referencecapacitor circuit 14 provides one charge package to the integrator input15. By the charge package, the comparator input voltage VIN is decreasedby a predetermined voltage difference. Since the comparator inputvoltage VIN is still higher than the comparator switching point, thecomparator signal SC again provides the first logical value, and afurther charge package is generated by the reference capacitor circuit14. This procedure is repeated until the comparator input voltage VIN isreduced by a charge package such that the comparator input voltage VINdrops below the comparator switching point. Therefore, the comparatorsignal SC obtains the second logical value indicating that thecomparator input voltage VIN is lower than the comparator switchingpoint.

For charging the reference capacitor 40, the second and the thirdreference switch 42, 44 are set in a conducting state and the first andthe fourth reference switch 41, 45 are set in a non-conducting state byreference control signals S1 to S4. For providing the charge package tothe integrator input 15, the second and the third reference switch 42,44 are set in a non-conducting state and the first and the fourthreference switch 41, 45 are set in a conducting state by the referencecontrol signals S1 to S4. The charge package has a charge value QREF:

QREF=VR1·CREF,

wherein VR1 is the voltage value of the first reference voltage and CREFis the capacitance value of the reference capacitor 40. The chargepackage has the opposite polarity than the photocurrent IP.

As can be seen in FIG. 2, at the end of the start phase A, thecomparator input voltage VIN is only slightly below the comparatorswitching point. In the example shown in FIG. 2, the comparatorthreshold voltage VCT that is equal to the comparator switching pointhas the value of 1.0 V. Advantageously, the starting point of the LTFmachine 10 is well-defined and independent of external light conditionsthat may influence the photocurrent IP. Thus, the output of theamplifier 26 of the integrator 12 which is equal to the comparator inputvoltage VIN is well-defined and independent of external lightconditions.

In the measuring phase B, the photodiode 11 provides the photocurrent IPto the integrator input 15 and thus the comparator input voltage VINrises. At the point of time when the comparator input voltage VIN has avalue higher or identical with the comparator switching point, thecomparator signal SC generates a pulse. The pulse in the comparatorsignal SC triggers the control circuit 21 to provide one charge packageby the reference capacitor circuit 14 to the integrator input 15. Thus,the comparator input voltage VIN is decreased. The rise of thecomparator input voltage VIN caused by the photocurrent IP, the pulsesof the comparator signal SC and the triggering of the referencecapacitor circuit 14 is repeated until the end of the measuring phase B.

The start phase A has a predetermined duration TA. The measuring phase Bhas a predetermined integration duration TB. The number of pulsesgenerated during the measuring phase B is a function of the value of thephotocurrent IP and thus of the light received by the photodiode 11. Theoutput signal SOUT of the control circuit 21 may be equal to thecomparator signal SC in the measuring phase B. A frequency f of thecomparator signal SC, and thus of the output signal SOUT, can becalculated according to the following equation:

f=N/TB,

wherein N is the number of pulses during the measuring phase B and TB isthe integration duration.

As can be seen in FIG. 2, the comparator signal SC may be realized as apulsed signal. Thus, the comparator SC obtains the first logical valueonly for a predetermined duration. Otherwise the comparator SC obtainsthe second logical value.

The comparator input voltage VIN has a value at the end of the startphase A and during the measuring phase B according to the followingequation:

VCT−ΔV≤VIN≤VCT,

wherein VCT is a value of the comparator threshold voltage which isequal to the comparator switching point and ΔV is a difference voltagevalue. The difference voltage value ΔV is the voltage difference whichcan be obtained by a single charge package provided by the referencecapacitor circuit 14. A duration between the start of the measuringphase B and the first pulse is in general smaller than a durationbetween two pulses, since the comparator input voltage VIN does notstart with the value VIN=VCT−ΔV at the beginning of the measuring phaseB. At the end of the start phase A, a difference between the comparatorinput voltage VIN and the comparator threshold voltage VCT is equal to astart error ER. Advantageously, the start error ER has a very low value.

The measuring phase B can be named integration cycle or LTF integrationcycle. The integration duration TB is equal to a measurement duration.According to FIG. 2, the integrator starting point is set to a levelabove the comparator switching point and the defined charge, which isalso used during the active LTF integration time, brings the integratorlevel—namely the comparator input voltage VIN—down to the comparatorswitching point in a defined time, and independent from the externallight conditions, before the measuring phase B starts.

By performing the start phase A, an undefined error is avoided and apossible error may amount to a maximum 1 LSB error and can be furtherreduced by using smaller charge steps which can be directly controlledwith the reference voltage provided to the reference capacitor 40. Forexample, the second reference voltage VR2 may be used in the start phaseA and the first reference voltage VR1 may be used in the measuring phaseB. The second reference voltage VR2 is smaller than the first referencevoltage VR1. Alternatively, the reference capacitor obtain a secondcapacitance value in the start phase A and a first capacitance value inthe measuring phase B. The second capacitance value is smaller than thefirst capacitance value. Thus, the charge value QREF of one chargepackage is smaller in the start phase A in comparison to the measuringphase B.

Advantageously, the charge steps which bring the integrator level downto the comparator switching point are provided with the integrator 12already settled and in a closed loop condition. Without the start phaseA, the starting point is only found by charging the integrator capacitor27 to the comparator switching point and then connecting the chargedintegrator capacitor 27 to an amplifier 26 which has not been in aclosed loop condition previously.

In the LTF machine 10 illustrated in FIGS. 1A and 1B, the pulses of thecomparator signal SC are counted for a certain amount of time namely theintegration duration TB. The reference capacitor 40 together with thefirst or the second reference voltage VR1, VR2 defines the charge thatis counted during the integration duration TB.

The first to the fourth reference switches 41, 42, 44, 45 are controlledby the control circuit 21 that brings the defined charge into theintegrator capacitor 27 or takes it out. The control circuit 21 maycomprise a state machine that generates the reference control signals S1to S4 for the switches 41, 42, 44, 45. The further integrator switch 29and the de-charging switch 24 are used to define roughly the startingvoltage for integration. This starting voltage can be seen at begin ofthe start phase A.

The first and the second switch 22, 23 are used to connect anddisconnect the photodiode 11 from the inverting input of the amplifier26 at the beginning and at the end of integration that means at thetransition from the start phase A to the measuring phase B as well as atthe end of the measuring phase B. When the first switch 22 is set in aconducting state, than the second switch 23 is set in a non-conductingstate. Correspondingly, when the first switch 22 is set in anon-conducting state, than the second switch 23 may be set in aconducting state.

In FIG. 2, simulation results are shown. At the beginning, the smallsteps bring the integrator 12 down to the comparator threshold withdefined steps (the amplifier 26 is already in closed loop condition).The switch control signal SW5 of the second switch 23 shows when thelight sensor arrangement 10 becomes active from the defined startingpoint to generate the output signal SOUT.

The start point for integration can be well defined. With this definedstarting point, the error generated for periodic sampling time isfurther reduced, where the same method is used as for the starting pointjust in the other direction.

There may be a rest charge counter operating in a rest charge measuringphase after the end of the measuring phase B. The photodiode 11 isdisconnected from the integrator input 15 and a defined amount of chargeis added to the integrator 12 as long as the integrator 12 reaches thestarting point for integration. This defined charge is counted up to theintegrator threshold and gives further bits of information. The opticalsensor arrangement 10 detects at which integrator level the opticalsensor arrangement 10 stops at the end of the integration cycle B. Thus,a further error is avoided.

In the rest charge measuring phase, the integration is quite simplewhere the supplies has to be exchanged for the reference capacitorcircuit 14: Instead of applying the reference voltage AVSS to the fourthreference switch 45 and of the first reference voltage VR1 to the thirdreference switch 44, the first reference voltage VR1 is applied to thefourth reference switch 45 and the reference voltage AVSS is provided tothe third reference switch 44. To get a higher resolution for theresidual charge counting, the first reference voltage VR1 has to bedivided by a factor n or has to be smaller than the originally usedcharge or a smaller reference capacitor 40 is used to reduce the chargepackage size.

For example, the second reference voltage VR2 generated as shown in FIG.1B is provided via the fifth reference switch 64 to the referencecapacitor 40. Thus, the smaller reference voltage VR2 is used to detectthe rest charge. The reference switches 41, 42, 44, 45 are controlledsuch the charge package has the same polarity than the photocurrent IP.The number of these charge packages are counted by the rest chargecounter until the comparator input voltage VIN reaches the comparatorswitching point. A high rest charge results in a small number.

FIG. 3 shows an exemplary embodiment of a timing diagram of the opticalsensor arrangement 10. In the start phase A, the comparator inputvoltage VIN is undefined. The comparator input voltage VIN obtains avalue near to the comparator threshold voltage VCT only accidently. Forexample, the comparator input voltage VIN may have a value that is thecomparator threshold voltage VC minus the start error ER. The starterror ER has a high value. In this case, the period between the start ofthe measuring phase B and the first pulse is longer than a durationbetween two pulses. Thus, at least one pulse is lost in comparison tothe signals shown in FIG. 2, e.g. two pulses are lost. The chargepackages in FIGS. 2 and 3 are equal.

Without the start phase A, the starting point of the LTF integrator 12is not well defined due to phenomena of charge injection, amplifiersettling etc.. The starting point as shown in FIG. 3 is below thecomparator switching point of the LTF machine and requires a certainamount of light to generate the first pulse. In order to minimise theerror, wait times are introduced before the LTF machine starts countingthe pulses. Especially for applications with low light conditions, thiswait time should be avoided, since the defined starting point of theoptical sensor arrangement 10 is a function of the external light.

The direction where the integrator 12 starts is changed in FIG. 3 incomparison to FIG. 2. Without start phase A, an undefined time is neededbefore the first pulses will start.

In an arrangement without the start phase A as described in FIGS. 1A, 1Band 2, the photo current IP of the photodiode 11 defines a wait timeuntil the arrangement can start with the LTF integration cycle B. Forlow light conditions, the wait time can be too short and the arrangementhas a negative offset, or in other words, has a high uncertainty whenthe first pulse in the LTF machine is generated, which is an error inabsolute counts. If more machines are working in parallel, this errordirectly acts as an error in channel matching and this error will beseen for post processing. These errors are avoided by the start phase Aas shown in FIG. 2.

1. An optical sensor arrangement, comprising: a photodiode, anintegrator with an integrator input coupled to the photodiode, acomparator with a first input coupled to an integrator output of theintegrator, and a reference capacitor circuit that is coupled to theintegrator input and is designed to provide a charge package to theintegrator input, wherein in a start phase, charge packages are providedto the integrator input, until a comparator input voltage at the firstinput of the comparator crosses a comparator switching point.
 2. Anoptical sensor arrangement according to claim 1, comprising a firstswitch that couples the photodiode to the integrator input.
 3. Anoptical sensor arrangement according to claim 2, wherein in the startphase, the first switch is set in a non-conducting state, and in ameasuring phase, the first switch is set in a conducting state.
 4. Anoptical sensor arrangement according to claim 1, comprising a secondswitch that couples the photodiode to a reference potential terminal. 5.An optical sensor arrangement according to claim 1, wherein thereference capacitor circuit is designed to selectively provide at leasttwo different charge values of the charge package to the integratorinput.
 6. An optical sensor arrangement according to claim 1, whereinthe reference capacitor circuit comprises a reference capacitor.
 7. Anoptical sensor arrangement according to claim 6, wherein the referencecapacitor is controllable and can obtain at least two differentcapacitance values.
 8. An optical sensor arrangement according to claim6, wherein the reference capacitor circuit comprises: a first referenceswitch coupling a first electrode of the reference capacitor to theintegrator input, a second reference switch coupling the first electrodeof the reference capacitor to a reference terminal, a third referenceswitch coupling a second electrode of the reference capacitor to areference source terminal and a fourth reference switch coupling thesecond electrode of the reference capacitor to the reference terminal.9. An optical sensor arrangement according to claim 8, wherein thereference capacitor circuit is configured to selectively provide atleast two different reference voltages to the reference source terminal.10. An optical sensor arrangement according to claim 1, wherein theintegrator comprises an amplifier having an input coupled to theintegrator input and an output coupled to the integrator output, andwherein the integrator comprises a integrator capacitor that is coupledbetween the input of the amplifier and the output of the amplifier. 11.An optical sensor arrangement according to claim 10, wherein theintegrator comprises an integrator switch coupling the integratorcapacitor to the output of the amplifier.
 12. An optical sensorarrangement according to claim 11, wherein the integrator comprises afurther integrator switch coupling a node between the integratorcapacitor and the integrator switch to a voltage terminal.
 13. Anoptical sensor arrangement according to claim 1, comprising ade-charging switch coupling the integrator input to a referencepotential terminal.
 14. An optical sensor arrangement according to claim1, wherein a comparator threshold voltage is applied to a second inputof the comparator for setting the comparator switching point.
 15. Amethod for light sensing, comprising: in a start phase, providing chargepackages by a reference capacitor circuit to an integrator input of anintegrator, until a comparator input voltage at a first input of acomparator crosses a comparator switching point, wherein the first inputof the comparator is coupled to an integrator output of the integrator,and in a measuring phase, providing a photo current of a photodiode tothe integrator input.
 16. An optical sensor arrangement, comprising: aphotodiode, an integrator with an integrator input, a first switch thatcouples the photodiode to the integrator input, a comparator with afirst input coupled to an integrator output of the integrator, and areference capacitor circuit that is coupled to the integrator input andis designed to provide a charge package to the integrator input, whereinin a start phase, charge packages are provided to the integrator input,until a comparator input voltage at the first input of the comparatorcrosses a comparator switching point, wherein a measuring phase followsthe start phase, and wherein in the measuring phase, the photodiodeprovides a photocurrent to the integrator input.